作者：金志权,张幸儿
出版社：电子工业出版社
格式: AZW3, DOCX, EPUB, MOBI, PDF, TXT
计算机专业英语教程(第5版)试读：
内容简介
本书为普通高等教育“十一五”国家级规划教材，旨在使读者了解计算机领域的新进展，了解和掌握最新和常用的专业英语术语。期望读者通过本教程的学习，巩固和扩大计算机专业知识面，能培养和提高阅读与笔译专业英语文献资料的能力，并达到会看、会听、会说和会写的英语四会能力。
本书素材取自近年来国外计算机科学各个领域的最新教材、专著、论文和计算机网络信息。内容新颖、覆盖面广、结构合理、系统性强、可读性高。为了方便读者，本书配有光盘，内容包括单词汇总、缩略语与术语索引以及部分音频和视频素材等。为了方便教学，本书另配有教学资源，向采用本书作为教材的教师免费提供。
本书可以作为高等院校计算机专业的专业英语教材，也可供计算机专业人员或其他有兴趣的读者学习参考。
第5版前言
计算机的发展令人感叹，本《计算机专业英语教程》从第1版的200多页，到目前第5版的400多页，页数翻了一番。虽然没有像计算机摩尔定律指出的那样，芯片上的元件数量每18个月翻一番那么快，但如果只是不断加入新内容，书的篇幅将会越来越长。计算机专业英语教材是基础性的，同时它又必须反映计算机科学的当前最新发展，使读者了解计算机领域中当前最热门的术语和缩略语。再考虑到计算机英语又是实践性很强的课程，为此本教程第5版在内容上作了如下的更新和调整。
1. 补充新课文，删除偏理论的、内容较深的课文，并适当调整章节，使内容安排上更为系统、合理和实用。
增加3.1 Computer programming，原10.2换为Spanning tree，原11.2换为Set theory，原Unit 12和Unit 13改为3个Unit，并增加ERP，原13.2换新内容的E-Business，原14.2换新内容的UML，增加17.3 Middleware。
2. 增加如下一些缩略语和新术语。● UEFI、LED、SATA、AOP、SNS、LTE、WSN● Quantum computer（量子计算机）、All in one（一体机）、
Groupware（群件）、Wikipedia（维基百科全书）、
YouTube（YouTube网站）、Facebook（面谱网站）、Micro-
blogging（微博）、Twitter（Twitter网站）、Internet of
Things（物联网）、Ajax、Cookie、Virtualization（虚拟化）、
Cloud computing（云计算）
3. 加强英语四会能力的培养。
英语四会是指会看、会听、会说、会写。为了提高听力，第4版提供了视听材料，广受欢迎。一些读者更希望提供课文朗读材料。因此本版增加了课文朗读，每个单元两篇课文朗读放在光盘中。另外，为了培养学生英语写作的能力，这一版在每个Unit中增加了中译英练习，加上听力练习，这样每个Unit后面都有四种练习，分别对应看、听、说、写。希望读者通过学习能提高英语的四会能力。
4. 在编排风格上本版稍作了一点调整，即，课文中单词第一次出现时用斜体标出。
为了便于读者查阅，第5版另配有光盘，其内容包括：● 单词汇总● 缩略词、术语索引● 参考文献● 视频素材● 每个Unit配有2篇课文的英文朗读材料● 前几版中所被删除的课文
本版保持了前四版的编排格式和基本风格。各校教师可根据自己的具体情况，因材施教，在每一个Unit里挑选课文进行教学。本书每个Unit都给出了听、说、读、写四种练习题。英语口语练习，可结合所列题目，组识学生进行课堂小组讨论或讲述。为了方便教学，本书另配有教学资源，内容包含电子教案、中译英练习题参考答案、视频素材的参考原文、若干课文参考译文、以及授课建议，向采纳本书作为教材的教师免费提供（获取方式：登录电子工业出版社华信资源网www.hxedu.com.cn或电话联系010-88254485）。
全书共分17章，第1、2、4、5、6、8、10、16、17章由金志权编写，第3、7、9、11、12、13、14、15章由张幸儿编写。彼此进行了互审。本书的电子教案由济南大学张景祥编写制作。
在此感谢对本书的编写给予帮助的南京大学陈佩佩、李存珠、陆钟楠、张福炎、李宣东、邵栋、黄皓、宋健建等老师、南京大学外国语学院王守成、杨治中、侯焕谬、张子清等老师、南京师范大学顾铁成老师。感谢张凌绮、Jimmy Jin、Amanda Fang、Steven Fang在课文朗读、视听素材收集和整理上给予的支持。感谢天津大学计算机科学与技术学院戴维迪博士的关心与支持。同时还要感谢丁正全、张万华、韩杰等提供的帮助。在此我们一并表示诚挚的感谢。
限于作者水平，书中难免会有不妥和错误之处，敬请读者批评指正。
反馈意见请发邮件至：jinzq@software.nju.edu.cn; zhangxr0@sina.com。编 者于南京大学Unit 1Hardware Ⅰ1.1 A Closer Look at the Processor and Primary Storage
We have learned that all computers have similar capabilities and perform essentially the same functions, although some might be faster than others. We have also learned that a computer system has input, output, storage, and processing components; that the processor is the “intelligence” of a computer system; and that a single computer system may have several processors. We have discussed how data are represented inside a computer system in electronic states called bits. We are now ready to expose the inner workings of the nucleus of the computer system—the processor.
The internal operation of a computer is interesting, but there really is no mystery to it. The mystery is in the minds of those who listen to hearsay and believe science-fiction writer. The computer is a nonthinking electronic device that has to be plugged into an electrical power source, just like a toaster or a lamp.
Literally hundreds of different types of computers are marketed by scores of manufacturers[1]. The complexity of each type may vary considerably, but in the end each processor, sometimes called the central processing unit or CPU，has only two fundamental sections：the control unit and the arithmetic and logic unit. Primary storage also plays an integral part in the internal operation of a processor. These three—primary storage, the control unit, and the arithmetic and logic unit—work together. Let's look at their functions and the relationships between them.
Unlike magnetic secondary storage devices, such as tape and disk, primary storage has no moving parts. With no mechanical movement, data can be accessed from primary storage at electronic speeds, or close to the speed of light. Most of today's computers use DRAM（Dynamic Random-Access Memory）technology for primary storage. A state-of-the-art DRAM chip about one eighth the size of a postage stamp[2] can store about 256,000,000 bits, or over 25,600,000 characters of data!
Primary storage, or main memory, provides the processor with temporary storage for programs and data. All programs and data must be transferred to primary storage from an input device（such as a VDT）or from secondary storage（such as a disk）before programs can be executed or data can be processed. Primary storage space is always at a premium；therefore, after a program has been executed, the storage space it occupied is reallocated to another program awaiting execution.
Figure 1-1 illustrates how all input/output（I/O）is “read to” or “written from” primary storage. In the figure, an inquiry（input）is made on a VDT. The inquiry, in the form of a message, is routed to primary storage over a channel（such as a coaxial cable）. The message is interpreted, and the processor initiates action to retrieve the appropriate program and data from secondary storage[3]. The program and data are “loaded”, or moved, to primary storage from secondary storage. This is a nondestructive read process. That is, the program and data that are read reside in both primary storage（temporarily）and secondary storage（permanently）. The data are manipulated according to program instructions, and a report is written from primary storage to a printer.Figure 1-1 Interaction Between Primary Storage and Computer System Components All programs and data must be transferred from an input device or from secondary storage before programs can be executed and data can be processed. During processing, instructions and data are passed between the various types of internal memories, the control unit, and the arithmetic and logic unit. Output is transferred to the printer from primary storage
A program instruction or a piece of data is stored in a specific primary storage location called an address. Addresses permit program instructions and data to be located, accessed, and processed. The content of each address is constantly changing as different programs are executed and new data are processed.
Another name for primary storage is random-access memory, or RAM. A special type of primary storage, called read-only memory（ROM），cannot be altered by the programmer. The contents of ROM are “hard-wired”（designed into the logic of the memory chip）by the manufacturer and can be “read only”. When you turn on a microcomputer system, a program in ROM automatically readies the computer system for use. Then the ROM program produces the initial display screen prompt.
A variation of ROM is programmable read-only memory（PROM）. PROM is ROM into which you, the user, can load “read-only” programs and data. Once a program is loaded to PROM, it is seldom, if ever, change[4]. However, if you need to be able to revise the contents of PROM, there is EPROM，erasable PROM. Before a write operation, all the storage cells must be erased to the same initial state.
A more attractive form of read-mostly memory is electrically erasable programmable read-only memory（EEPROM）. It can be written into at any time without erasing prior contents; only the byte or bytes addressed are updated[5].
The EEPROM combines the advantage of nonvolatility with the flexibility of being updatable in place[6]，using ordinary bus control, address, and data lines.
Another form of semiconductor memory is flash memory（so named because of the speed）. Flash memory is intermediate between EPROM and EEPROM in both cost and functionality. Like EEPROM, flash memory uses an electrical erasing technology. An entire flash memory can be erased in one or a few seconds, which is much faster than EPROM. In addition, it is possible to erase just blocks of memory rather than an entire chip. However, flash memory does not provide byte-level erasure[7]. Like EPROM, flash memory uses only one transistor per bit, and so achieves the high density of EPROM.Cache Memory
Program and data are loaded to RAM from secondary storage because the time required to access a program instruction or piece of data from RAM is significantly less than from secondary storage. Thousands of instructions or pieces of data can be accessed from RAM in the time it would take to access a single piece of data from disk storage[8]. RAM is essentially a high-speed holding area for data and programs. In fact, nothing really happens in a computer system until the program instructions and data are moved to the processor. This transfer of instructions and data to the processor can be time-consuming, even at microsecond speeds. To facilitate an even faster transfer of instructions and data to the processor, most computers are designed with cache memory. Cache memory is employed by computer designers to increase the computer system throughput（the rate at which work is performed）.
Like RAM, cache is a high-speed holding area for program instructions and data. However, cache memory uses SRAM（Static RAM）technology that is about 10 times faster than RAM and about 100 times more expensive. With only a fraction of the capacity of RAM, cache memory holds only those instructions and data that are likely to be needed next by the processor. Two types of cache memory appear widely in computers. The first is referred to as internal cache and is built into the CPU chip. The second, external cache, is located on chips placed close to the CPU chip. A computer can have several different levels of cache memory. Level 1 cache is virtually always built into the chip. Level 2cache used to be external cache but is now typically also built into the CPU like level 1 cache.Figure 1-2 Inside a typical PC system unit. The system unit houses the CPU, memory, and other important pieces of hardwareWords and Expressions
processor［'prəusesə］ n. 处理机
primary storage 主存储器
bit［bit］ n. 位，二进制位，比特
hearsay［'hiəsei］ n. 传闻，谣传
scores of 许多
CPU 中央处理机
control unit 控制部件，控制器
arithmetic and logic unit 算术逻辑部件
integral parts 不可缺的部分，组成部分
tape and disk 这里指磁带和磁盘
DRAM 动态随机存取存储器，SRAM 静态随随机存取存储器
a state of the art（the state of the art）目前工艺水平，最新发展水平
chip［t∫ip］ n. 芯片
VDT（Video Display Terminal）视频显示终端
secondary storage 辅助存储器，二级存储器
at a premium 非常珍贵
reallocate［ri:'æləkeit］ v. 重新分配
capacity［kə'pæsiti］ n. 容量
coaxial cable 同轴电缆
program and data 程序和数据
instruction［in'strʌkʃən］ n. 指令
register［'reʤistə］ n. 寄存器，记录，登记簿，登记，注册
location［ləu'keiʃən］ n. 单元，位置
RAM 随机存取存储器；ROM 只读存储器
hardwired adj. 硬连线，硬件（线路）实现的
EPROM 可擦可编程只读存储器
read-mostly adj. 以读为主的，大多数为读的
EEPROM 电可擦可编程ROM
nonvolatility［nɔn'vɔlə'tiliti］ n. 非易失性
updatable［'ʌpˌdeitəbl］ adj. 可修改的
in place 在适当的地方，存在
semiconductor［semikən'dʌktə］ n. 半导体
flash memory 闪存
functionality［'fʌŋkʃəneiliti］ n. 功能，功能性，函数性
byte-level 字节级
cache［kæ∫］ n. 高速缓存，隐藏
throughput［'θru(:)'put］ n. 吞吐量，生产量，生产能力
be referred to as 称做，叫做
virtually［'və:tjuəli］ adv. 事实上，实际上
house［haus］ vt. 存放，给……房子住
expansion［iks'pænʃən］ n. 扩充，开展
peripheral［pə'rifərəl］ adj. 外围的；n. 外围设备，外设
slot［slɔt］ n. 插槽，槽
power supply 电源，供电
system board 系统板=mother board 主板
storage bay 存储机架
floppy［'flɔpi］ n. 软盘，floppy drive 软盘驱动器
Zip drive 见2.4节Notes 2Notes
[1]这里are marketed意为“被销售”，literally译为“不加夸张地讲，确实地”。全句可译为：不加夸张地讲，市场上有几百种不同类型的计算机在销售。
[2]about one eighth the size of a postage stamp是介词短语，修饰前面的DRAM chip，即约1/8邮票大小（的）。
[3]retrieve the appropriate…意为“取出所需的……”，initiate译为“启动，初始化”。本句译为：消息被解释，处理机从辅助存储器取出所需的程序和数据。本句的上一句中route译为“发送，路由”。全句译为：查询以消息的形式通过通道（像同轴电缆）发送到主存储器。
[4]it is seldom, if ever, changed中插入的if ever是常见用法，可译为“它简直从不改变”。
[5]only the byte or bytes addressed中addressed修饰前面的the byte or bytes。本句可译为：EEPROM在任何时候都可写入，不需擦除原先内容，且只更新寻址到的字节或多个字节。
[6]being updatable in place是of的介词短语。in place是指需要更新的地方，因此短语的含义是“可更新、需要更新的字节”。本句可译为：EEPROM把非易失性优点和可更新、需更新的地方的灵活性结合起来，修改时使用普通的总线控制线、地址线和数据线。
[7]本句说的“闪存不提供字节级的擦除”（flash memory does not provide byte-level erasure）是针对EEPROM可对字节修改，即提供字节级的擦除；而EPROM若要修改字节，则必须先擦除整块EPROM的原先内容，所以三种存储的擦除单位分别是：EPROM整个存储器Flash 块（类似于硬盘）memoryEEPROM字节（可能多个字节）
目前的移动U盘，数码相机等的闪存卡：CF卡（Compact Flash），Smart Media卡，xD卡（eXtreme Digital），记忆棒（Memory Stick），SD卡（Secure Digital）等都用闪存。
[8]it would take to access…是定语从句，修饰前面的the time，其前面省略了关系代词that。it是引导词，作形式主语，真实主语是动词不定式to access…。access译为“访同，存取”。全句译为：从磁盘存储器上存取单个数据所花的时间，可以从RAM中存取几千条指令或数据。
注：本节主要介绍计算机的CPU，主存及闪存等内容。1.2 Bus Interconnection
A bus is a communication pathway connecting two or more devices. A key characteristic of a bus is that it is a shared transmission medium[9]. Multiple devices connect to the bus, and a signal transmitted by any one device is available for reception by all other devices attached to the bus. If two devices transmit during the same time period, their signals will overlap and become garbled. Thus, only one device at a time can successfully transmit.
Typically, a bus consists of multiple communication pathways, or lines. Each line is capable of transmitting signals representing binary 1 and binary 0. Over time, a sequence of binary digits can be transmitted across a single line. Taken together[10]，several lines of a bus can be used to transmit binary digits simultaneously（in parallel）. For example, an 8-bit unit of data can be transmitted over eight bus lines.
Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy[11]. A bus that connects major computer components（processor, memory, I/O）is called a system bus.
A system bus consists, typically, of from 50 to 100 separate lines. Each line is assigned a particular meaning or function. Although there are many different bus designs, on any bus the lines can be classified into three functional groups（Figure 1-3）：data, address, and control lines. In addition, there may be power distribution lines that supply power to the attached modules[12].Figure 1-3 Bus Interconnection Scheme
The data lines provide a path for moving data between system modules. These lines, collectively, are called the data bus. The data bus typically consists of 8，16，or 32 separate lines, the number of lines being referred to as the width of the data bus[13]. Because each line can carry only 1 bit at a time, the number of lines determines how many bits can be transferred at a time. The width of the data bus is a key factor in determining overall system performance.
The address lines are used to designate the source or destination of the data on the data bus. For example, if the processor wishes to read a word of data from memory, it puts the address of the desired word on the address lines. Clearly, the width of the address bus determines the maximum possible memory capacity of the system.
The control lines are used to control the access to and the use of the data and address lines[14]. Because the data and address lines are shared by all components, there must be a means of controlling their use. Control signals transmit both command and timing information between system modules. Timing signals indicate the validity of data and address information. Command signals specify operations to be performed.
Most computer systems enjoy the use of multiple buses, generally laid out in a hierarchy[15]. A typical high-performance architecture is shown in Figure 1-4. There is a local bus that connects the processor to a cache controller, which is in turn connected to a system bus that supports main memory. The cache controller is integrated into a bridge that connects to the high-speed bus[16]. This bus supports connections to high-speed LANs, video and graphics workstation controller, as well as interface controller to local peripheral buses, including SCSI, and FireWire[17]. Lower-speed devices are still supported off an expansion bus, with an interface buffering traffic between the expansion bus and the high-speed bus[18].Figure 1-4 Example Bus ConfigurationPCI Express pumps up performance
In the past decade，PCI has served as the dominant I/O architecture for PCs and server, carrying data generated by microprocessors, network adapters, graphics cards and other subsystems to which it is connected[19]. However, as the speed and capabilities of computing components increase, PCI's bandwidth limitations and the inefficiencies of its parallel architecture increasingly have become bottlenecks to system performance.
PCI is a unidirectional parallel bus architecture in which multiple adapters must contend for available bus bandwidth. Although performance of the PCI interface has been improved over the years, problems with signal skew（when bits of data arrive at their destination too late），signal routing and the inability to lower the voltage or increase the frequency, strongly indicate that the architecture is running out of steam[20]. Additional attempts to improve its performance would be costly and impractical in response, a group of vendors, including some of the largest and most successful system developers in the industry, unveiled an I/O architecture dubbed PCI Express（initially called Third Generation I/O, or 3GIO）.
PCI Express is a point-to-point switching architecture that creates high-speed, bidirectional links between a CPU and system I/O（the switch is connected to the CPU by a host bridge）. Each of these links can encompass one or more “lanes” comprising four wires-two for transmitting data and two for receiving data. The design of these lanes enables the use of lower voltages（resulting in lower powers usage），reduces electromagnetic emissions, eliminates signal skew, lowers costs through simpler design and generally improves performance.
In its initial implementation，PCI Express can yield transfer speeds of 2.5 Gbit/sec in each direction, on each lane. By contrast, the version of the PCI architecture that is most common today, PCI-X1.0，offers 1 Gbit/sec in throughput. PCI Express cards are available in four-or eight-lane configurations（called x4 and x8）. An x4 PCI Express card can provide as much as 20 Gbit/sec in throughput, while an x8 PCI Express card can offer up to 40 Gbit/sec in throughput.
Earlier attempts to create a new PCI architecture failed in part because they required so many changes to the system and application software. Drivers, utilities and management applications all would have to be rewritten. PCI Express developers removed the dependency on new operating system support, letting PCI-compatible drivers and applications run unchanged on PCI Express hardware[21].A bus for the future
Developers are working on increasing the scalability of PCI Express. While current server and desktop systems support PCI Express adapters and graphics cards with up to eight lanes（x8），the architecture will support as many as 32 lanes（x32）in the future.
The first Fibre Channel host bus adapters were designed to support four lanes instead of eight lanes, in part because server developers had designed their systems with four-lane slots. As even more bandwidth is required, implementing an eight-lane design potentially could double the performance, provided there were no other bottlenecks in the system.
This scalability, along with the expected doubling of the speed of each lane to 5 Gbit/sec, should keep PCI Express a viable solution for designers for the foreseeable future[22].
PCI Express is a significant improvement over PCI and is well on its way to becoming the new standard for PCs, servers and more. Not only can it lower costs and improve reliability, but it also significantly can improve performance. Applications such as music and video-streaming, video on demand, VoIP and data storage will benefit from these improvements.Words and Expressions
bus［bʌs］ n. 总线
pathway［'pa:θwei］ n. 通路，路径
interconnection［intə(:)kə'nekʃən］ n. 互连
share［ʃɛə］ n. vt. 共享，分享，均分
overlap［'əuvə'læp］ v. 重叠，交迭
garble［'ga:bl］ vt. 混淆，篡改
over time 一段时间里
in parallel 并行地
hierarchy［'haiəra:ki］ n. 分层（结构），层次
collectively［kə'lektivli］ adv. 合在一起，集体地
timing［'taimiŋ］ n. 时序，定时，同步
controller［kən'trəulə］ n. 控制器
integrated［'intigreitid］ adj. 集成
SCSI 参见2.4节后的Terms
traffic［'træfik］ n. 通信流量，信息量，交通
pump up［pʌmp］ v. 使充气，扩大，增加，这里可译为提升，提高
PCI（Peripheral Component Interconnect）外设部件互连
architecture［'a:kitektʃə(r)］ n. 体系结构，结构
server［'sə:və］ n. 服务器
adapter［ə'dæptə］ n. 适配器；network adapter 网卡，网络适配器
bandwidth［'bændwidθ］ n. 带宽
bottleneck［'bɔtlnek］ n瓶颈
unidirectional［ju:nidi'rek∫ənəl］ adj. 单向（性）的；bidirectional［bai～］双向的
interface［'intəfeis］ n. 接口，界面
skew［skju:］ adj. 歪斜的，偏的
route［ru:t］ n. 路线，路程，通道；v. 路由，发送
run out of steam 失去势头，失去热情
试读结束[说明：试读内容隐藏了图片]